论文信息 - A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes

A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes

An application that takes advantage of FeRAM characteristics is replacing current DRAM, which then becomes high-performance nonvolatile RAM cache. This improves system performance for many kinds of computer systems, including mobile PCs, cellular phones, digital video products, and storage systems such as SSDs. However, the highest capacity in nonvolatile RAMs that allow frequent cache reads and writes is limited to 64Mb [1,2]. The maximum read bandwidth is limited to 400MB/s [3] and the write bandwidth is limited to 200MB/s [1] in nonvolatile memories reported to date.

[1] S.Y. Lee,et al. 130 nm-technology, 0.25 μm2, 1T1C FRAM cell for SoC (system-on-a-chip)-friendly applications , 2007, 2007 IEEE Symposium on VLSI Technology.

[2] Daniele Vimercati,et al. A 65 nm 1 Gb 2b/cell NOR Flash With 2.25 MB/s Program Throughput and 400 MB/s DDR Interface , 2008, IEEE Journal of Solid-State Circuits.

[3] Yukihito Oowaki,et al. A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive , 1999 .

[4] S. Shiratake,et al. A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.