Joining the design and mask flows for better and cheaper masks

Today's design-manufacturing interfaces have only minimal information exchange. Lack of information on either side leads to under-performance due to too much guardbanding, and increased mask cost and increased turnaround time due to over-correction. In this work we present techniques that simultaneously utilize design and manufacturing information to improve mask quality and reduce mask cost.

[1]  Sachin S. Sapatnekar,et al.  Standby power optimization via transistor sizing and dual threshold voltage assignment , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

[2]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[3]  Fook-Luen Heng,et al.  Merits of cellwise model-based OPC , 2004, SPIE Advanced Lithography.

[4]  David Blaauw,et al.  Statistical estimation of leakage current considering inter- and intra-die process variation , 2003, ISLPED '03.

[5]  Rajendran Panda,et al.  Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Mark C. Johnson,et al.  Design and optimization of low voltage high performance dual threshold CMOS circuits , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[7]  Puneet Gupta,et al.  Design sensitivities to variability: extrapolations and assessments in nanometer VLSI , 2002, 15th Annual IEEE International ASIC/SOC Conference.

[8]  Kaushik Roy,et al.  Gate leakage reduction for scaled devices using transistor stacking , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Puneet Gupta,et al.  A cost-driven lithographic correction methodology based on off-the-shelf sizing tools , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[10]  Sachin S. Sapatnekar,et al.  Standby power optimization via transistor sizing and dual threshold voltage assignment , 2002, ICCAD 2002.

[11]  Andrew B. Kahng,et al.  Manufacturing-aware physical design , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[12]  Ravi Nair,et al.  Generation of performance constraints for layout , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  M.L. Rieger,et al.  Layout design methodologies for sub-wavelength manufacturing , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[14]  Stephen Hsu,et al.  Understanding the forbidden pitch phenomenon and assist feature placement , 2002, SPIE Advanced Lithography.

[15]  Majid Sarrafzadeh,et al.  Optimal integer delay budgeting on directed acyclic graphs , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[16]  Puneet Gupta,et al.  Selective gate-length biasing for cost-effective runtime leakage control , 2004, Proceedings. 41st Design Automation Conference, 2004..