High-Speed Programmable Logic Array Adders

Programmable Logic Array (PLA) adders are described which perform an addition in one cycle with a single pass through a PLA and require a reasonable number of product terms for an 8-, 16-, or even a 32-bit adder. The PLA features two-bit input decoders feeding an AND array followed by an OR array whose outputs are pairwise Exclusive-ORed. Carry-look-ahead adder equations, adapted to the PLA to require relatively few product terms, are adjusted for maximum sharing of product terms. The number of unique product terms is a relative measure of one of the physical dimensions of the PLA. Equations for contiguous sum bits are grouped into strings, each using a common input carry. A procedure optimally assigns sum bits to strings to further minimize the total number of unique product terms. The methods are extended to PLAs with decoders of increased inputs and substantially reduced product terms. They can serve as dedicated macro functions on a chip, using special decoders relevant to adders. As a result, the other PLA dimension comprising the number of outputs from all input decoders increases only moderately, and can even decrease, with larger decoders. Finally, the PLA adder can be further substantially compressed by splitting the OR array into two parts such that a row of the AND array is shared between two product terms, and an OR array column is shared between two sums of product terms.