Challenges in power-ground integrity

With the advance of semiconductor manufacturing, EDA, and VLSI design technologies, circuits with increasingly higher speed are being integrated at an increasingly higher density. This trend causes correspondingly larger voltage fluctuations in the on-chip power distribution network due to IR-drop, L di/dt noise, or LC resonance. Therefore, power-ground integrity becomes a serious challenge in designing future high-performance circuits. In this paper, we introduce power-ground integrity, addressing its importance, verification methodology, and problem solution.

[1]  P. Larsson.  Resonance and damping in CMOS circuits with on-chip decoupling capacitance , 1998 .

[2]  Lawrence T. Pileggi,et al.  Modeling magnetic coupling for on-chip interconnect , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[3]  Rajendran Panda,et al.  Hierarchical analysis of power distribution networks , 2000, DAC.

[4]  S. Chowdhury.  Optimum Design of Reliable IC Power Networks Having General Graph Topologies , 1989, 26th ACM/IEEE Design Automation Conference.

[5]  Thomas D. Burd,et al.  Design issues for Dynamic Voltage Scaling , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[6]  Rajendran Panda,et al.  Model and analysis for combined package and on-chip power grid simulation , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[7]  J. Black.  Electromigration failure modes in aluminum metallization for semiconductor devices , 1969 .

[8]  Sani R. Nassif,et al.  Fast power grid simulation , 2000, Proceedings 37th Design Automation Conference.

[9]  David D. Ling,et al.  Power Supply Noise Analysis Methodology For Deep-submicron Vlsi Chip Design , 1997, Proceedings of the 34th Design Automation Conference.

[10]  Burton M. Leary,et al.  A 200 MHz 64 b dual-issue CMOS microprocessor , 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[11]  Leon O. Chua,et al.  Computer-Aided Analysis Of Electronic Circuits , 1975 .

[12]  Sheldon X.-D. Tan,et al.  Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  John Lillis,et al.  Interconnect Analysis and Synthesis , 1999 .

[14]  Ernest S. Kuh,et al.  Power and ground network topology optimization for cell based VLSIs , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[15]  Sheldon X.-D. Tan,et al.  Fast power/ground network optimization based on equivalent circuit modeling , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[16]  Sheldon X.-D. Tan,et al.  Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings , 1999, DAC '99.

[17]  S. Samudrala,et al.  System, process, and design implications of a reduced supply voltage microprocessor , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[18]  Hao Ji,et al.  How to efficiently capture on-chip inductance effects: introducing a new circuit element K , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).