Unified Framework for Logic Diagnosis

Abstract This paper presents a unified diagnosis method targeting most of the fault models used in practice today. This framework is intended to be used to diagnose faulty behaviors in nanometric circuits for which the classical stuck-at fault model is far to cover all realistic failures. The method is based on an Effect-Cause approach which relies on the two following main operations. The first one is based on critical path tracing (CPT) [4] and consists in identifying critical lines in the Circuit Under Test (CUT) which can be the source of observed errors. The second one consists in allocating a set of possible fault models to each critical line, so that root causes of failures can be finally determined. The main advantage of this method is that it does not need to explicitly consider each fault model during the diagnosis process. 1. Introduction Failure analysis is an important operation, which may impact the circuit design and the fabrication process and has a growing role in fast yield ramping. Failure analysis first relies on a logical diagnosis aiming at reducing the potential faulty subparts of the circuit before using more sophisticated physical tools in order to precisely locate and identify the defect. This logical diagnosis process is based on the knowledge of the structure of the circuit, the applied test vectors and the responses to these vectors provided by the tester (test data log). The objective of logic diagnosis is to locate and identify failures leading to a CUT erroneous behaviour. Information provided by the diagnosis process is therefore used to guide the circuit physical observation during failure analysis. Thus, the efficiency of the failure analysis depends on the resolution of the diagnosis process. There are two types of diagnosis approaches, namely