High Performance UDP/IP 40Gb Ethernet Stack for FPGAs

As Ethernet bandwidths continue to increase, the challenge of meeting these increased throughput requirements remains a non-trivial problem, especially when the underlying IP is implemented on a reconfigurable fabric like an FPGA. In order to meet the higher throughput rates, it becomes necessary to have wider data paths, operating at much higher frequencies - both of which add complexity to a Network Stack design implemented on an FPGA. Wider data paths necessitate routing a larger number of wires across the underlying fabric, while higher operating frequencies make it more difficult to attain timing closure. Apart from the above mentioned challenges, it is important to keep the footprint for such an infrastructural module as small as possible, in order to guarantee that maximum amount of resources are available for the rest of the user logic. This paper puts forth a resource optimized 40Gb Ethernet Network Stack design, with support for UDP/IP, along with support for ARP and ICMP protocols, and a host of other features. Timing closure is targeted at 250 MHz, with Xilinx UltraScale family of devices.