A new RC design for mixed-grain based dynamically reconfigurable architectures

Reconfigurable mixed grain architectures have been demonstrated to be efficient and flexible for data parallel and computation-intensive applications. In this paper we present the design of a new Reconfigurable Cell (RC) based on a mixed-grain architecture. The architecture delivers a gate-level implementation of the Reconfigurable Logic Unit (RLU) focusing on the ALU implementation. The investigation of the new reconfigurable cell has been performed on 0.35, 0.25 and 0.18 micron CMOS technology. Experimental results include synthesis implementation and optimization data as well as performances analysis performed on some benchmark applications. On the average ReCoM results more than 6 times better performant than alternative reconfigurable architecture.

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