FPGA implementation of DES encryption arithmetic with dynamic key management

The thesis puts forward a hardware design scheme of dynamic key management based on the traditional DES encryption arithmetic. The scheme will re-configure the key based on the analysis of the principium of DES encryption and the weak relativity between the generation of sub-key and the critical arithmetic. The DES arithmetic adopts the methodology of preferential resources and sets up the pipelining architecture inside the round-function. Thus it can improve the speed of whole system. The thesis implements the operation of round-function and key-transform function based on the FPGA. This can reduce the logic complication of adjacent pipeline and implement the re -configuration design of DES arithmetic on FPGA. Finally, the thesis finishes the whole function simulation and test analysis based on the design, argument of the correction of the whole system.