An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits

A method to estimate the coverage of path delay faults of a given test set, without enumerating paths, is proposed. The method is polynomial in the number of lines in the circuit, and thus allows circuits with large numbers of paths to be considered under the path delay fault model. Several levels of approximation, with increasing accuracy and increasing polynomial complexity, are proposed. Experimental results are presented to show the effectiveness and accuracy of the estimate in evaluating the path delay fault coverage. Combining this nonenumerative estimation method with a test generation method for path delay faults would yield a cost effective method to consider path delay faults in large circuits, which are beyond the capabilities of existing test generation and fault simulation procedures, that are based on enumeration of paths. >

[1]  Shimon Even,et al.  Graph Algorithms , 1979 .

[2]  Kaushik Roy,et al.  Issues in logic synthesis for delay and bridging faults , 1990, IEEE International Symposium on Circuits and Systems.

[3]  André Ivanov,et al.  Accelerated path delay fault simulation , 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

[4]  Kaushik Roy,et al.  Synthesis of delay fault testable combinational logic , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[5]  Michael H. Schulz,et al.  Advanced automatic test pattern generation techniques for path delay faults , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[6]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  S. M. Reddy,et al.  On the design of path delay fault testable combinational circuits , 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.

[8]  Irith Pomeranz,et al.  SPADES: a simulator for path delay faults in sequential circuits , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[9]  Srinivas Devadas,et al.  Necessary and sufficient conditions for robust delay-fault testability of combinational logic circuits , 1990 .

[10]  Sudhakar M. Reddy,et al.  On the design of robust testable CMOS combinational logic circuits , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[11]  Kurt Keutzer,et al.  Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits , 1990, DAC '90.

[12]  Kenneth D. Wagner,et al.  The Error Latency of Delay Faults in Combinational and Sequential Circuits , 1985, ITC.

[13]  Sudhakar M. Reddy,et al.  On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Kurt Keutzer,et al.  Testability properties of multilevel logic networks derived from binary decision diagrams , 1991 .

[15]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[16]  Kurt Keutzer,et al.  Design of integrated circuits fully testable for delay-faults and multifaults , 1990, Proceedings. International Test Conference 1990.

[17]  Michael H. Schulz,et al.  Parallel Pattern Fault Simulation of Path Delay Faults , 1989, 26th ACM/IEEE Design Automation Conference.

[18]  Irith Pomeranz,et al.  ACHIEVING COMPLETE DELAY FAULT TESTABILITY BY EXTRA INPUTS , 1991, 1991, Proceedings. International Test Conference.

[19]  John J. Shedletsky,et al.  An Experimental Delay Test Generator for LSI Logic , 1980, IEEE Transactions on Computers.

[20]  M. Ray Mercer,et al.  The interdependence between delay-optimization of synthesized networks and testing , 1991, 28th ACM/IEEE Design Automation Conference.

[21]  S. Reddy,et al.  On the design of robust multiple fault testable CMOS combinational logic circuits , 1988, ICCAD 1988.

[22]  Jacob Savir,et al.  Random Pattern Testability of Delay Faults , 1988, IEEE Trans. Computers.

[23]  Kurt Keutzer,et al.  Testability-preserving circuit transformations , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[24]  Srinivas Devadas Delay test generation for synchronous sequential circuits , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[25]  Yashwant K. Malaiya,et al.  Testing for Timing Faults in Synchronous Sequential Integrated Circuits , 1983, International Test Conference.

[26]  S. Reddy,et al.  Synthesis of combinational logic circuits for path delay fault testability , 1990, IEEE International Symposium on Circuits and Systems.