A new series parallel switched multilevel dc-link inverter topology

Abstract The variable voltage and frequency requirements emphasize the need and elaborate the increasing trend of using multilevel inverters (MLI) in modern drives and utility applications. The MLIs carves out a nearly sinusoidal voltage from a stair case like waveform and the distortion level in the output voltage depends on the number of steps. Increased component count and extension of basic modulation strategies to the MLIs pose a bigger threat in the form layout size, cost and complexity of the gating circuits. These conflicting requirements force to explore different and or new configurations to meet the state of art necessities and it is this perspective a host of topologies keep emerging. Topologies based on multilevel dc-link inverter (MLDCLI) structure pioneer the component reduction and add benefits to suit economic and power quality considerations besides living up to technological innovation. The paper orients to develop a new variety of MLDCLI named series parallel switched multilevel dc-link inverter (SPMLDCLI) with a primary objective to arrive at reduced component count for a particular voltage level. By appropriately choosing a ratio for the voltage sources (V0:Vn) and connecting them in series/parallel, a particular level in the output voltage is generated and hence the name SPSMLDCLI. The performance of the topology is investigated through MATLAB based simulation over a range of viable modulation indices and validated using a prototype to propel its applicability in the present day context. The conventional sub harmonic pulse width modulation strategy (SHPWM) with pulse pattern suitable for SPSMLDCLI is considered.