A new method to achieve improved accuracy with IBIS models

IBIS (input/output buffer information specification) models are known to lack information regarding power and ground bounce resulting in incorrect simulations. In this paper, a novel solution to the problem is proposed making it possible to simulate IBIS models with available simulators and have a realistic chance at simulating simultaneous switching noise (SSN) that are present in most if not all high speed circuits. To demonstrate the solution, a CMOS voltage-mode driver circuit and a current-mode LVDS driver circuit are simulated using HSPICE and compared with equivalent circuits created with IBIS models of the same drivers. The IBIS models are created using the s2ibis tool from North Carolina State University.

[1]  A. Boni,et al.  LVDS I/O interface for Gb/s-per-pin operation in 0.35-/spl mu/m CMOS , 2001 .

[2]  P. Franzon,et al.  The development of a macro-modeling tool to develop IBIS models , 2003, Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710).

[3]  P. Franzon,et al.  SSN issues with IBIS models , 2004, Electrical Performance of Electronic Packaging - 2004.