Generic ILP versus specialized 0-1 ILP: an update

Optimized solvers for the Boolean Satisfiability (SAT) problem have many applications in areas such as hardware and software verification, FPGA routing, planning, etc. Further uses are complicated by the need to express "counting constraints" in conjunctive normal form (CNF). Expressing such constraints by pure CNF leads to more complex SAT instances. Alternatively, those constraints can be handled by Integer Linear Programming (ILP), but generic ILP solvers may ignore the Boolean nature of 0--1 variables. Therefore specialized 0--1 ILP solvers extend SAT solvers to handle these so-called "pseudo-Boolean" constraints.This work provides an update on the on-going competition between generic ILP techniques and specialized 0--1 ILP techniques. To make a fair comparison, we generalize recent ideas for fast SAT-solving to more general 0--1 ILP problems that may include counting constraints and optimization. Another aspect of our comparison is evaluation on 0--1 ILP benchmarks that originate in Electronic Design Automation (EDA), but that cannot be directly solved by a SAT solver. Specifically, we solve instances of the Max-SAT and Max-ONEs optimization problems which seek to maximize the number of satisfied clauses and the "true" values over all satisfying assignments, respectively. Those problems have straightforward applications to SAT-based routing and are additionally important due to reductions from Max-Cut, Max-Clique, and Min Vertex Cover. Our experimental results show that specialized 0--1 techniques tend to outperform generic ILP techniques on Boolean optimization problems as well as on general EDA SAT problems.

[1]  Donald W. Loveland,et al.  A machine program for theorem-proving , 2011, CACM.

[2]  George B. Dantzig,et al.  Linear programming and extensions , 1965 .

[3]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[4]  Michael Burstein,et al.  Hierarchical Wire Routing , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Edward A. Feigenbaum,et al.  Switching and Finite Automata Theory: Computer Science Series , 1990 .

[6]  Tracy Larrabee,et al.  Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Sanjeev Saxena,et al.  On Parallel Prefix Computation , 1994, Parallel Process. Lett..

[8]  Bart Selman,et al.  Noise Strategies for Improving Local Search , 1994, AAAI.

[9]  Henry Kautz,et al.  Noise Strategies for Local Search , 1994, AAAI 1994.

[10]  P. Barth A Davis-Putnam based enumeration algorithm for linear pseudo-Boolean optimization , 1995 .

[11]  Robert K. Brayton,et al.  Combinational test generation using satisfiability , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Hantao Zhang,et al.  An Efficient Algorithm for Unit Propagation , 1996 .

[13]  Roberto J. Bayardo,et al.  Using CSP Look-Back Techniques to Solve Real-World SAT Instances , 1997, AAAI/IAAI.

[14]  Joachim P. Walser Solving Linear Pseudo-Boolean Constraint Problems with Local Search , 1997, AAAI/IAAI.

[15]  Hantao Zhang,et al.  SATO: An Efficient Propositional Prover , 1997, CADE.

[16]  Bart Selman,et al.  Boosting Combinatorial Search Through Randomization , 1998, AAAI/IAAI.

[17]  Joost P. Warners,et al.  A Linear-Time Transformation of Linear Inequalities into Conjunctive Normal Form , 1998, Inf. Process. Lett..

[18]  Luis Miguel Silveira,et al.  Timing analysis using propositional satisfiability , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

[19]  Masahiro Fujita,et al.  Symbolic model checking using SAT procedures instead of BDDs , 1999, DAC '99.

[20]  Joao Marques-Silva,et al.  GRASP: A Search Algorithm for Propositional Satisfiability , 1999, IEEE Trans. Computers.

[21]  Joao Marques-Silva,et al.  Using Randomization and Learning to Solve Hard Real-World Instances of Satisfiability , 2000, CP.

[22]  Vasco M. Manquinho,et al.  On using satisfiability-based pruning techniques in covering algorithms , 2000, DATE '00.

[23]  M. Moskewicz,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[24]  Randal E. Bryant,et al.  Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW , 2001, DAC '01.

[25]  Inês Lynce,et al.  Stochastic Systematic Search Algorithms for Satisfiability , 2001, Electron. Notes Discret. Math..

[26]  Joonyoung Kim,et al.  SATIRE: A new incremental satisfiability engine , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[27]  Sanjeev Khanna,et al.  Complexity classifications of Boolean constraint satisfaction problems , 2001, SIAM monographs on discrete mathematics and applications.

[28]  Sharad Malik,et al.  Efficient conflict driven learning in a Boolean satisfiability solver , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[29]  Igor L. Markov,et al.  Faster SAT and smaller BDDs via common function structure , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[30]  Igor L. Markov,et al.  Solving difficult SAT instances in the presence of symmetry , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[31]  Randal E. Bryant,et al.  Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors , 2003, J. Symb. Comput..

[32]  sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[33]  Rob A. Rutenbar,et al.  A comparative study of two Boolean formulations of FPGA detailed routing constraints , 2001, IEEE Transactions on Computers.