Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals

In this work, an analytical model for estimation of width scalable architectural level leakage current of the 6T Static Random Access Memory (SRAM), considering its peripherals is proposed in 45nm technology. Based on the mode of operation of SRAM (read, write and idle phase), the width dependent leakage current is estimated at an early stage which reduces design time and aid to power management. Finally, a SRAM structure (i.e. rows and columns) dependent model has been evaluated. Referring circuit simulator (HSPICE) as golden result, the proposed model shows a high accuracy with error margin less than 5%. The results are 143,127 and 330 times faster than that achieved by HSPICE simulation in idle, read and write phase respectively.

[1]  Gurindar S. Sohi,et al.  A static power model for architects , 2000, MICRO 33.

[2]  Nikil D. Dutt,et al.  IDAP: a tool for high-level power estimation of custom array structures , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Li-Shiuan Peh,et al.  Leakage power modeling and optimization in interconnection networks , 2003, ISLPED '03.

[4]  Trevor York,et al.  Book Review: Principles of CMOS VLSI Design: A Systems Perspective , 1986 .

[5]  Nikil Dutt,et al.  Leakage Power Estimation in SRAMs , 2003 .

[6]  Nikil D. Dutt,et al.  Analytical models for leakage power estimation of memory array structures , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..

[7]  Vivek Tiwari,et al.  Topological analysis for leakage prediction of digital circuits , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[8]  Kevin Skadron,et al.  HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects , 2003 .

[9]  Rong Luo,et al.  Leakage Power Modeling Method for SRAM Considering Temperature, Supply Voltage and Bias Voltage , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.