A 250 MHz 5 W RISC microprocessor with on-chip L2 cache controller

This superscalar microprocessor is a 32b implementation of the PowerPC Architecture(TM) specification based on a micro-architecture designed for high performance and low power. Two instructions per cycle can be dispatched in this superscalar design. The processor includes dual 32kB 8-way instruction and data caches, a floating-point unit, two integer units, a branch unit, a load/store unit, and a system unit. An L2 tag and cache controller with a dedicated L2 bus interface are added to provide a low-cost L2 cache solution using commodity SRAMs for the data.