Via design optimisation for high speed device packaging

This paper presents the design and electrical characterization of a circular via hole applied to single and multi chip modules. A typical strip line-to-strip line configuration incorporating the via hole is designed, modelled and simulated using the Maxwell Strata mixed potential integration equation (MPIE)-based field solver. This configuration is modelled on a practical user-defined transmission line structure consisting of conductors of finite conductivity. We investigated the effects of three critical parameters, via hole diameter, ground plane opening and via height, on the frequency response. It is found that the via hole diameter should be minimized while the other two parameters should be maximized for better performance. This paper thus provides useful optimization criteria for circular vias, given the practical limitations of manufacturing technologies.

[1]  Roger F. Harrington,et al.  The excess capacitance of a microstrip via in a dielectric substrate , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  K. C. Gupta,et al.  EM-ANN models for microstrip vias and interconnects in dataset circuits , 1996 .

[3]  Daniël De Zutter,et al.  Capacitance of a circular symmetric model of a via hole including finite ground plane thickness , 1991 .

[4]  Tzyy-Sheng Horng,et al.  Via hole, bond wire and shorting pin modeling for multi-layered circuits , 1994, 1994 IEEE MTT-S International Microwave Symposium Digest (Cat. No.94CH3389-4).

[5]  Wolfgang J. R. Hoefer,et al.  Time domain analysis of via holes and shorting pins in microstrip using 3-D SCN TLM , 1993, 1993 IEEE MTT-S International Microwave Symposium Digest.

[6]  Raj Mittra,et al.  Characterizing the cylindrical via discontinuity , 1993 .

[7]  D. Zutter,et al.  Prediction of the excess capacitance of a via-hole through a multilayered board including the effect of connecting microstrips or striplines , 1994 .

[8]  Raj Mittra,et al.  Time domain electromagnetic analysis of a via in a multilayer computer chip package , 1992, 1992 IEEE Microwave Symposium Digest MTT-S.

[9]  F. Arndt,et al.  Efficient MPIE approach for the analysis of three-dimensional microstrip structures in layered media , 1997 .

[10]  F. Alessandri,et al.  Full-wave modeling of via hole grounds in microstrip by three-dimensional mode matching technique , 1992 .

[11]  Y. E. Yang,et al.  Modeling and analysis of vias in multilayered integrated circuits , 1993 .

[12]  R. Harrington,et al.  Quasi-static analysis of a microstrip via through a hole in a ground plane , 1988 .

[13]  T. Itoh,et al.  A hybrid full-wave analysis of via hole grounds using finite difference and finite element time domain methods , 1997, 1997 IEEE MTT-S International Microwave Symposium Digest.