Proving More Properties with Bounded Model Checking
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[1] Sharad Malik,et al. Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[2] A. Prasad Sistla,et al. Safety, liveness and fairness in temporal logic , 1994, Formal Aspects of Computing.
[3] Edmund M. Clarke,et al. Efficient generation of counterexamples and witnesses in symbolic model checking , 1995, DAC '95.
[4] Kenneth L. McMillan,et al. Interpolation and SAT-Based Model Checking , 2003, CAV.
[5] Tiziano Villa,et al. VIS: A System for Verification and Synthesis , 1996, CAV.
[6] Daniel Kroening,et al. Efficient Computation of Recurrence Diameters , 2003, VMCAI.
[7] Harald Ruess,et al. Bounded Model Checking and Induction: From Refutation to Verification (Extended Abstract, Category A) , 2003, CAV.
[8] Joël Ouaknine,et al. Completeness and Complexity of Bounded Model Checking , 2004, VMCAI.
[9] Armin Biere,et al. Symbolic Model Checking without BDDs , 1999, TACAS.
[10] Amir Pnueli,et al. Checking that finite state concurrent programs satisfy their linear specification , 1985, POPL.
[11] Bowen Alpern,et al. Defining Liveness , 1984, Inf. Process. Lett..
[12] Marco Pistore,et al. Improving the Encoding of LTL Model Checking into SAT , 2002, VMCAI.
[13] Viktor Schuppan,et al. Efficient reduction of finite state model checking to reachability analysis , 2004, International Journal on Software Tools for Technology Transfer.
[14] Pierre Wolper,et al. An Automata-Theoretic Approach to Automatic Program Verification (Preliminary Report) , 1986, LICS.
[15] Mary Sheeran,et al. Checking Safety Properties Using Induction and a SAT-Solver , 2000, FMCAD.
[16] Kavita Ravi,et al. A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles , 2000, FMCAD.
[17] Fabio Somenzi,et al. Efficient Büchi Automata from LTL Formulae , 2000, CAV.