Design methodology for the implementation of multidimensional circular convolution
暂无分享,去创建一个
[1] S. Winograd. On computing the Discrete Fourier Transform. , 1976, Proceedings of the National Academy of Sciences of the United States of America.
[2] Chaitali Chakrabarti,et al. VLSI Architectures for Multidimensional Transforms , 1991, IEEE Trans. Computers.
[3] Izidor Gertner,et al. VLSI Architectures for Multidimensional Fourier Transform Processing , 1987, IEEE Transactions on Computers.
[4] Kenneth C. Yeager,et al. 200-MHz superscalar RISC microprocessor , 1996, IEEE J. Solid State Circuits.
[5] Yukio Sugeno,et al. A Multiplier-Accumulator Macro for a 45 MIPS Embedded RISC Processor , 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.
[6] Vassilis Paliouras,et al. A VLSI design methodology for RNS full adder-based inner product architectures , 1997 .
[7] Alan V. Oppenheim,et al. Discrete-Time Signal Pro-cessing , 1989 .
[8] Kenneth Steiglitz,et al. Combinatorial Optimization: Algorithms and Complexity , 1981 .
[9] S. Kung,et al. VLSI Array processors , 1985, IEEE ASSP Magazine.
[10] J. Bu,et al. Systematic design of regular VLSI processor arrays , 1990 .
[11] Dan E. Dudgeon,et al. Multidimensional Digital Signal Processing , 1983 .