Enhancement of resolution in supply current based testing for large ICs

Current drawn by a static CMOS VLSI integrated circuit during quiescent periods is extremely small and is normally of the order of nanoamperes. However, it is remarkably susceptible to a number of failure modes. Many faults present in such ICs cause the quiescent power-supply current (IDDQ) to increase by several orders of magnitude. Some of these faults may not manifest as logical faults, and would not be detected by traditional IC test techniques. In large ICs, it may be hard to distinguish between larger IDDQ due to defects and elevated IDDQ due to normal parameter variations. A statistical characterisation of the problem is presented. This can be used to determine the optimal size of partitions. A new information compression scheme is presented which can significantly enhance resolution.<<ETX>>

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