Synthesizable ADCs are economically attractive as they enable low-cost rapid development of SoC; however, they are yet to achieve adequate performance to meet practical application specs. This paper presents a fully synthesized VCO-based $\Delta \Sigma $ modulator that built solely from digital standard cells and a few resistors. Leveraging time-domain techniques, the design is robust against circuit and layout imperfections, thus enabling a simple hierarchy-less synthesis approach without sacrificing performance. Fabricated in 40-nm CMOS, the prototype occupies only 0.01 mm2. It achieves 68.8 dB SNDR over 4-MHz BW while consuming 1.08 mW, displaying 60-fJ/step Walden FoM that matches with state-of-the-art manual-designed CTDSMs.