Execution interval analysis under resource constraints

Execution intervals are commonly used in high-level synthesis systems to identify the relation between operations and the cycle steps in which they possibly can be scheduled. These intervals are normally based on the ASAP (as soon as possible) and ALAP (as late as possible) values of operations under the assumption of unlimited resources. In this paper a novel and much more accurate execution interval analysis is presented for designs on which resource constraints are imposed. The analysis prunes the search space of schedulers without limiting the solution space and therefore enhances the quality of schedulers. The method is based on a bipartite graph matching formulation and runs in polynomial time. Well-known benchmarks show the positive effects of the approach on scheduling results and run times.

[1]  Alice C. Parker,et al.  The high-level synthesis of digital systems , 1990, Proc. IEEE.

[2]  Catherine H. Gebotys,et al.  Optimal VLSI Architectural Synthesis , 1992 .

[3]  Alberto Sangiovanni-Vincentelli,et al.  A note on bipartite graphs and pivot selection in sparse matrices , 1976 .

[4]  Miodrag Potkonjak,et al.  Resource driven synthesis in the HYPER system , 1990, IEEE International Symposium on Circuits and Systems.

[5]  G. De Micheli,et al.  A module selection algorithm for high-level synthesis , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[6]  Catherine H. Gebotys,et al.  Optimal VLSI Architectural Synthesis: Area, Performance and Testability , 1991 .

[7]  Minjoong Rim,et al.  Estimating lower-bound performance of schedules using a relaxation technique , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[8]  Wolfgang Rosenstiel,et al.  Automatic module allocation in high level synthesis , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[9]  D.D. Gajski,et al.  An algorithm for component selection in performance optimized scheduling , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[10]  A. H. Timmer,et al.  Module selection and scheduling using unrestricted libraries , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.