Explicit formulation of delays in CMOS data paths

An explicit formulation of the transient response of general combinational CMOS structures is presented, including load conditions and driving waveforms. Based on data-path decomposition in unidirectional elementary cells, timing models developed here allow an analytic formulation of the real temporal behaviour of inverters, transmission gate arrays, and general CMOS gates. Validation is obtained through a comparison between delay times, calculated following this formulation, and values deduced from SPICE simulations, for a large range of inverters and gate structures with different configuration ratios and tapering factors. Results are shown to be in excellent agreement with less than 10% discrepancy. >

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