Novel bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced isolation (SITOS) and gate to shallow-well contact (SSS-C) processes for ultra low power dual gate CMOS
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T. Matsuoka | T. Fukushima | S. Kakimoto | Y. Sato | H. Kotaki | M. Nakano | K. Adachi | K. Sugimoto