Amplitude demodulation based on synchronized sampling by a PLL circuit
暂无分享,去创建一个
[1] Ahmed Ashry,et al. A 4th Order 3.6 GS/s RF $\Sigma\Delta$ ADC With a FoM of 1 pJ/bit , 2013 .
[2] Bernard Lacaze,et al. Lowpass/bandpass signal reconstruction and digital filtering from nonuniform samples , 2015, 2015 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).
[3] Michael P. Flynn,et al. A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF , 2012, 2012 IEEE International Solid-State Circuits Conference.
[4] Ammar B. Kouki,et al. Direct RF Sampling GNSS Receiver Design and Jitter Analysis , 2012 .
[5] Michael P. Flynn,et al. A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF , 2014, IEEE Journal of Solid-State Circuits.
[6] W. Marsden. I and J , 2012 .
[7] D. Allstot,et al. A QPLL-timed direct-RF sampling band-pass ΣΔ ADC with a 1.2 GHz tuning range in 0.13 µm CMOS , 2011, 2011 IEEE Radio Frequency Integrated Circuits Symposium.
[8] Gordana Jovanovic-Dolecek,et al. On the use of passive circuits to implement LC-based band-pass CT ΣΔ modulators , 2015, 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS).
[9] Ahmed Ashry,et al. A 4th Order 3.6 GS/s RF /spl Sigma//spl Delta/ ADC With a FoM of 1 pJ/bit , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.
[10] C. Azeredo-Leme,et al. Clock Jitter Effects on Sampling: A Tutorial , 2011, IEEE Circuits and Systems Magazine.
[11] Tadashi Maeda,et al. A Low-IF/Zero-IF Reconfigurable Analog Baseband IC With an I/Q Imbalance Cancellation Scheme , 2011, IEEE Journal of Solid-State Circuits.
[12] Ahmad Mirzaei,et al. Highly Integrated and Tunable RF Front Ends for Reconfigurable Multiband Transceivers: A Tutorial , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.
[13] James B. Y. Tsui,et al. Direct bandpass sampling of multiple distinct RF signals , 1999, IEEE Trans. Commun..