论文信息 - ISC Processor with Pseudo Vector Processing Feature

ISC Processor with Pseudo Vector Processing Feature

A novel architectural extension, in which floatingpoint a&t are transterred directly from main memory to jloating-point registers, has been successfully implemented in a superscalar RISC processor. This extension allows main memory access throughput of I .2 Gbytels, and efective perjonnance reaches 267 MPLOPS (89% of the peakper$ormance) for typical floating-point applications. The processor utilizes 0.3-micron 4-level metal CMOS technology with 2.5 V power supply and contains 3.9 million transistors in 15.7 mm x 15.7 mm die size. Only 4.5% of the die area is used for the extension. Pipeline stage optimization and swreboardbased dependency check method allow the extension to be realized without affecting the operating j?equency.

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