Hardware / Software Partitioning and Scheduling Algorithms for Dynamically Reconfigurable Architectures

The use of dynamically reconfigurable logic (DRL) in the design of embedded systems has added a new dimension to the hardware/software co-synthesis problem. The spatial computing advantage and silicon reuse offered by DRL comes at the cost of reconfiguration latency which has to be effectively managed in order to optimize the system performance and power consumption. The initial attempts at leveraging DRL only aimed at optimizing the system performance, while recently power consumption minimization is also being researched. Another dimension is the dynamic run-time scheduling of DRL for applications having intrinsically dynamic behavior, as opposed to static scheduling explored by majority of the approaches. Nevertheless, the results obtained by applying these approaches show that the use of DRL promises reduction in system costs and increase in performance as compared to solutions which do not use DRL.