FAST 기반 특징 점 추출 가속기의 구현

This paper presents the feature point extraction accelerator based on digital logics. The proposed scheme for real-time applications is designed by utilizing the FAST-9 algorithm of E. Rosten. The presented acceleration scheme can be developed by using approximately 2,215 Flip Flops, 3,315 LUTs, 1,750 Slices, and 17 Block RAMs in Xilinx Vertex Ⅳ FX FPGA. The proposed scheme is verified that it can extract about 2,000 features from the image with 640x480 pixels during 4ms.