A 0.75-V 58-MHz 340-μW SOTB-65nm 32-point DCT Implementation Based on Fixed-rotation Adaptive CORDIC
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[1] Weiwei Shen,et al. A Unified 4/8/16/32-Point Integer IDCT Architecture for Multiple Video Coding Standards , 2012, 2012 IEEE International Conference on Multimedia and Expo.
[2] Seongsoo Lee,et al. 2-D Large Inverse Transform (16×16, 32×32) for HEVC (High Efficiency Video Coding) , 2012 .
[3] Chuohao Yeo,et al. Efficient Integer DCT Architectures for HEVC , 2014, IEEE Transactions on Circuits and Systems for Video Technology.
[4] Trong-Thuc Hoang,et al. Low-resource low-latency hybrid adaptive CORDIC with floating-point precision , 2015, IEICE Electron. Express.
[5] Hideharu Amano,et al. Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[6] Aaron Stillmaker,et al. Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm , 2017, Integr..
[7] Trong-Thuc Hoang,et al. Minimum adder-delay architecture of 8/16/32-point DCT based on fixed-rotation adaptive CORDIC , 2018, IEICE Electron. Express.