FPGA implementation of a hardware XTEA light encryption engine in co-design computing systems

In the era of viruses and hackers targeting high-tech information transported across the Internet, security is becoming a paramount goal. A cryptographic system is a method of hiding information where only the person owning the related secret key can open it. There are several types of cryptography algorithms that differ from each other in security complexity, the size of key and words operated on, and the processing time. We analyse the development of a light and relatively fast hardware implementation of the Extended Tiny Encryption Algorithm (XTEA). This paper presents a hardware accelerated XTEA Encryption-Decryption system based on FPGA (Field Programmable Gate Array) logic devices, namely the Altera Cyclone-V FPGA assisted with a NIOS II soft-core basic processor. The NIOS II processor behaved as a software execution platform, while the FPGA hardware approach synthesised the XTEA algorithm using VHDL code. In addition, a co-design approach is considered where the NIOS II processor co-processed with the XTEA Hardware accelerator module is tested in practice. A throughput of over 113 Mb/s is reached and an 26x speedup was recorded in regard to the soft processor implementation. In addition, hardware replication of the basic XTEA circuit has been shown to be a realistic method to increase the throughput to an even much higher rate.