Modeling of Topologies of Interconnection Networks based on Multidimensional Multiplicity

Modern SoCs are becoming more complex with the integration of heterogeneous components (IPs). For this purpose, a high performance interconnection medium is required to handle the complexity. Hence NoCs come into play enabling the integration of more IPs into the SoC with increased performance. These NoCs are based on the concept of Interconnection networks used to connect parallel machines. In response to the MARTE RFP of the OMG, a notation of multidimensional multiplicity has been proposed which permits to model repetitive structures and topologies. This report presents a modeling methodology based on this notation that can be used to model a family of Interconnection Networks called Delta Networks which in turn can be used for the construction of NoCs.

[1]  Howard Jay Siegel,et al.  Analysis Techniques for SIMD Machine Interconnection Networks and the Effects of Processor Address Masks , 1977, IEEE Transactions on Computers.

[2]  Martin Collier.  A systematic analysis of equivalence in multistage networks , 2002 .

[3]  B. Cordan.  An efficient bus architecture for system-on-chip design , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[4]  Marshall C. Pease,et al.  The Indirect Binary n-Cube Microprocessor Array , 1977, IEEE Transactions on Computers.

[5]  Abdou Youssef,et al.  Interconnection Networks for High-Performance Parallel Computers , 1994 .

[6]  Holger Giese,et al.  Component Templates for Dependable Real-Time Systems , 2004 .

[7]  Paul Budnik,et al.  The Organization and Use of Parallel Memories , 1971, IEEE Transactions on Computers.

[8]  Howard Jay Siegel,et al.  Using the multistage cube network topology in parallel supercomputers , 1989 .

[9]  Gilad Bracha,et al.  Adding wildcards to the Java programming language , 2004, SAC '04.

[10]  David S. Wise.  Compact Layouts of Banyan/FFT Networks , 1981 .

[11]  Dietmar Tutsch,et al.  MINSimulate - A MULTISTAGE INTERCONNECTION NETWORK SIMULATOR , 2003 .

[12]  Howard Jay Siegel,et al.  Interconnection networks for large-scale parallel processing: theory and case studies (2nd ed.) , 1985 .

[13]  Peter Fettke,et al.  Model Driven Architecture (MDA) , 2003, Wirtsch..

[14]  Stefan Hanenberg,et al.  Designing Aspect-Oriented Crosscutting in UML , 2002 .

[15]  Dharma P. Agrawal,et al.  Performance Analysis of Single Stage Interconnection Networks , 1991, IEEE Trans. Computers.

[16]  Pierre Boulet,et al.  UML2 Profile for Modeling Controlled Data Parallel Applications , 2006, FDL.

[17]  Arnaud Cuccuru.  Modélisation unifiée des aspects répétitifs dans la conception conjointe logicielle/matérielle des systèmes sur puce à hautes performances , 2005 .

[18]  Ahmad Chadi Aljundi,et al.  Une méthodologie multi-critères pour l'évaluation de performance appliquée aux architectures de réseaux d'interconnexion multi-étages , 2004 .

[19]  Allan Borodin,et al.  Routing, merging and sorting on parallel models of computation , 1982, STOC '82.

[20]  Jean-Philippe Babau,et al.  From MDD Concepts to Experiments and Illustrations , 2007 .

[21]  Patrick G. Sobalvarro,et al.  Probabilistic Analysis of Multistage Interconnection Network Performance , 1992 .

[22]  Mohan Kumar,et al.  Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor , 1997, IEEE Trans. Parallel Distributed Syst..

[23]  Janak H. Patel.  Performance of Processor-Memory Interconnections for Multiprocessors , 1981, IEEE Transactions on Computers.

[24]  Axel Jantsch,et al.  Networks on chip , 2003 .

[25]  Laxmi N. Bhuyan,et al.  High-performance computer architecture , 1995, Future Gener. Comput. Syst..

[26]  Rocco Moretti,et al.  Model Driven Architecture (MDA) , 2007 .

[27]  Bjarne Stroustrup,et al.  C++ Programming Language , 1986, IEEE Softw..

[28]  James E. Smith,et al.  Statistical simulation of symmetric multiprocessor systems , 2002, Proceedings 35th Annual Simulation Symposium. SS 2002.

[29]  Charles Clos,et al.  A study of non-blocking switching networks , 1953 .

[30]  Duncan H. Lawrie,et al.  Access and Alignment of Data in an Array Processor , 1975, IEEE Transactions on Computers.

[31]  Mohand Tahar Kechadi.  Un modèle de fonctionnement désordonné pour les systèmes multiprocesseurs pipelines vectoriels à mémoires partagées : définition, modélisation et proposition d'architecture , 1993 .

[32]  Janak H. Patel,et al.  Processor-memory interconnections for multiprocessors , 1979, ISCA '79.