Area-efficient architectures for the Viterbi algorithm. I. Theory

In the state-parallel implementation of the Viterbi algorithm, one add-compare-select (ACS) unit is devoted to each state in the treillis. A systematic approach to partitioning, scheduling, and mapping N trellis states to P ACSs, where N>P, is presented here. The area saving of this architecture comes from the reduced number of ACSs and interconnection wires. The design of the ACS, path metric storage, and routing network is discussed in detail. The proposed architecture creates internal parallelism due to the ACS sharing, which can be exploited to increase the throughput rate by pipelining. Consequently, the architecture offers a favorable (smaller) area-time product, compared to the state-parallel implementation. >

[1]  V. Benes.  Optimal rearrangeable multistage connecting networks , 1964 .

[2]  Gerhard Fettweis,et al.  Parallel Viterbi algorithm implementation: breaking the ACS-bottleneck , 1989, IEEE Trans. Commun..

[3]  Leslie G. Valiant,et al.  A fast parallel algorithm for routing in permutation networks , 1981, IEEE Transactions on Computers.

[4]  David G. Messerschmitt,et al.  Algorithms and architectures for concurrent Viterbi decoding , 1989, IEEE International Conference on Communications, World Prosperity Through Communications,.

[5]  G. David Forney,et al.  Maximum-likelihood sequence estimation of digital sequences in the presence of intersymbol interference , 1972, IEEE Trans. Inf. Theory.

[6]  Thomas Kailath,et al.  Locally connected VLSI architectures for the Viterbi algorithm , 1988, IEEE J. Sel. Areas Commun..

[7]  Tse-Yun Feng,et al.  On a Class of Multistage Interconnection Networks , 1980, IEEE Transactions on Computers.

[8]  V. Benes.  On rearrangeable three-stage connecting networks , 1962 .

[9]  Jr. G. Forney,et al.  The viterbi algorithm , 1973 .

[10]  Andrew J. Viterbi,et al.  Error bounds for convolutional codes and an asymptotically optimum decoding algorithm , 1967, IEEE Trans. Inf. Theory.

[11]  P. Glenn Gulak,et al.  VLSI Structures for Viterbi Receivers: Part I-General Theory and Applications , 1986, IEEE J. Sel. Areas Commun..

[12]  John M. Cioffi,et al.  A block processing method for designing high-speed Viterbi detectors , 1989, IEEE International Conference on Communications, World Prosperity Through Communications,.

[13]  John P. Fishburn,et al.  Quotient Networks , 1982, IEEE Transactions on Computers.