A tiq-based cmos flash a/d converter for system-on-chip applications
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[1] Kari Halonen,et al. A single-amplifier 6-bit CMOS pipeline A/D converter for WCDMA receivers , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).
[2] M. Vertregt,et al. A 6b 1.6 Gsample/s flash ADC in 0.18 /spl mu/m CMOS using averaging termination , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[3] B. Razavi,et al. An 8-bit 150-MHz CMOS A/D converter , 1999, IEEE Journal of Solid-State Circuits.
[4] Bang-Sup Song,et al. A 1-V 6-b 50-MSamples/s current-interpolating CMOS ADC , 2000, IEEE Journal of Solid-State Circuits.
[5] Y. Tamba,et al. A CMOS 6 b 500 MSample/s ADC for a hard disk drive read channel , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
[6] Michael J. Demler. High-speed analog-to-digital conversion , 1991 .
[7] R. Jacob Baker,et al. CMOS Circuit Design, Layout, and Simulation , 1997 .
[8] Michael P. Flynn,et al. A "digital" 6-bit ADC in 0.25-μm CMOS , 2002 .
[9] Kyusun Choi,et al. Comparator Generation and Selection for Highly Linear CMOS Flash Analog-to-Digital Converter , 2003 .
[10] Jose E. Franca,et al. Systematic Design for Optimisation of Pipelined Adcs , 2001 .
[11] Myung-Jun Choe,et al. An 8 b 100 MSample/s CMOS pipelined folding ADC , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).
[12] General Terms Design , 2022 .
[13] Ramón González Carvajal,et al. A 1.1 V low-power /spl Sigma//spl Delta/ modulator for 14-b 16 kHz A/D conversion , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).
[14] Kyusun Choi,et al. CMOS flash analog-to-digital converter for high speed and low voltage applications , 2003, GLSVLSI '03.
[15] Kyusun Choi,et al. Future-ready ultrafast 8bit CMOS ADC for system-on-chip applications , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).
[16] Baher Haroun. 18.2 An Embedded 0.8V/480µW 6b/22MHz Flash ADC in 0.13µm Digital CMOS Process using Nonlinear Double-Interpolation Technique , 2002 .
[17] C.J.B. Fayomi,et al. A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 /spl mu/m CMOS technology , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).
[18] Phillip E Allen,et al. CMOS Analog Circuit Design , 1987 .
[19] Bernard Loriferne. Analog-digital and digital-analog conversion , 1982 .
[20] Maxim Staff. INL/DNL measurements for high-speed analog-to-digital converters (ADCs) , 2001 .
[21] Jaume Segura,et al. A variable threshold voltage inverter for CMOS programmable logic circuits , 1998 .
[22] Bang-Sup Song. Analog front-end macro circuit design , 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).
[23] S. Tsukamoto,et al. A CMOS 6b 400 M sample/s ADC with error correction , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).
[24] Kyusun Choi,et al. A 1-GSPS CMOS flash A/D converter for system-on-chip applications , 2001, Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems.
[25] Shen-Iuan Liu,et al. An 8-bit 10 MS/s folding and interpolating ADC using the continuous-time auto-zero technique , 2001 .
[26] Kyusun Choi,et al. Fat tree encoder design for ultra-high speed flash A/D converters , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..
[27] Shanthi Pavan,et al. A Dual-Mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D Converter in a 0.25- m Digital CMOS Process , 2000 .
[28] M. Vertregt,et al. A 2.5-V 12-b 54-Msample/s 0.25-μm CMOS ADC in 1-mm2 with mixed-signal chopping and calibration , 2001, IEEE J. Solid State Circuits.
[29] M. Gloanec,et al. 1 GHz GaAs ADC building blocks , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.
[30] Friedel Gerfers,et al. A design strategy for low-voltage low-power continuous-time /spl Sigma//spl Delta/ A/D converters , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[31] B. Brar,et al. A monolithic 4 bit 2 GSps resonant tunneling analog-to-digital converter , 1997, GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. 19th Annual Technical Digest 1997.
[32] Carver Mead,et al. Analog VLSI and neural systems , 1989 .
[33] M. Vertregt,et al. A 6b 1.6 Gsample/s flash ADC in 0.18 μm CMOS using averaging termination , 2002 .
[34] Toshio Kumamoto,et al. A 10 bit 20 MS/s 3 V supply CMOS A/D converter , 1994 .
[35] Howard C. Luong,et al. Power optimization for pipeline analog-to-digital converters , 1999 .
[36] R. C. Taft,et al. A 100-MS/s 8-b CMOS subranging ADC with sustained parametric performance from 3.8 V down to 2.2 V , 2001 .
[37] T. Van Duzer,et al. Fully parallel superconducting analog-to-digital converter , 1993, IEEE Transactions on Applied Superconductivity.
[38] Alfi Moscovichi. High Speed A/D Converters: Understanding Data Converters Through Spice , 2000 .
[39] M. Wolfe,et al. A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-/spl mu/m digital CMOS process , 2000, IEEE Journal of Solid-State Circuits.
[40] J. Burghartz,et al. A 4 b 8 GSample/s A/D converter in SiGe bipolar technology , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
[41] Brian Black. Analog-to-Digital Converter Architec- tures and Choices for System Design , 1999 .
[42] Kwangho Yoon,et al. A 6 b 500 MSample/s CMOS flash ADC with a background interpolated auto-zeroing technique , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
[43] E.K.F. Lee,et al. A 1-V, 8-bit successive approximation ADC in standard CMOS process , 2000, IEEE Journal of Solid-State Circuits.
[44] G. Geelen,et al. A 6 b 1.1 GSample/s CMOS A/D converter , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[45] W. Ellersick,et al. A serial-link transceiver based on 8 GSample/s A/D and D/A converters in 0.25 /spl mu/m CMOS , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
[46] John B. Hughes,et al. A low voltage 8-bit, 40 MS/s switched-current pipeline analog-to-digital converter , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).
[47] Kari Halonen,et al. 1-V 9-bit pipelined switched-opamp ADC , 2001 .
[48] A. Boni,et al. A novel coding scheme for the ROM of parallel ADCs, featuring reduced conversion noise in the case of single bubbles in the thermometer code , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).
[49] Michel Steyaert,et al. A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).
[50] E. K. Gannett,et al. THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS , 1965 .
[51] Kyusun Choi,et al. Design method and automation of comparator generation for flash A/D converter , 2002, Proceedings International Symposium on Quality Electronic Design.
[52] J. Yamada,et al. 1 V power supply, low-power consumption A/D conversion technique with swing-suppression noise shaping , 1994 .
[53] Chuan Yi Tang,et al. A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..
[54] Kyusun Choi,et al. A power and resolution adaptive flash analog-to-digital converter , 2002, ISLPED '02.
[55] Michel J. Declercq,et al. A 640 mW high accuracy 8-bit 1 GHz flash ADC encoder , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).