Switch Design for Soft Interconnection Networks

Soft on-FGPA interconnection networks are gaining increasing importance since they simplify the integration of heterogeneous components and parallelize, at the same time, the communication among the modules of the system. The switches are the basic building blocks of such networks, and their design critically affects the performance of the whole system. The way data traverse each switch is governed by the operation of the arbiter and the crossbar’s multiplexers that need to be efficiently mapped on the FPGA fabric. The LUT mapping of wide multiplexers has been well investigated, either by enhancing the features of the corresponding mapping algorithms or by fully exploiting the structure and the additional features of the FPGA logic blocks. However, the combined mapping of an arbiter and a multiplexer as a whole to the programmable logic and interconnect of an FPGA has not been sufficiently explored. This chapter aims at bridging this gap; we will first present and compare the traditional implementations that are based on separate allocator and crossbar modules, and then we will expand the design space by presenting new soft macros that can handle allocation and multiplexing concurrently.

[1]  Laxmi N. Bhuyan,et al.  The impact of link arbitration on switch performance , 1999, Proceedings Fifth International Symposium on High-Performance Computer Architecture.

[2]  Giorgos Dimitrakopoulos,et al.  Fast arbiters for on-chip network switches , 2008, 2008 IEEE International Conference on Computer Design.

[3]  Mike Galles.  Spider: a high-speed network interconnect , 1997, IEEE Micro.

[4]  William J. Dally,et al.  Allocator implementations for network-on-chip routers , 2009, Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis.

[5]  Bill Lin,et al.  Design and implementation of high-speed symmetric crossbar schedulers , 1999, 1999 IEEE International Conference on Communications (Cat. No. 99CH36311).

[6]  Yuval Tamir,et al.  Symmetric Crossbar Arbiters for VLSI Communication Switches , 1993, IEEE Trans. Parallel Distributed Syst..

[7]  Hideharu Amano,et al.  Prediction router: Yet another low latency on-chip router architecture , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[8]  William J. Dally,et al.  A delay model and speculative architecture for pipelined routers , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[9]  Dhiraj K. Pradhan,et al.  A Routing-Aware ILS Design Technique , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[11]  Mark Jones,et al.  Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip , 2008, FPL.

[12]  William J. Dally.  Virtual-channel flow control , 1990, ISCA '90.

[13]  Nick McKeown,et al.  Designing and implementing a fast crossbar scheduler , 1999, IEEE Micro.

[14]  Sakir Sezer,et al.  Generic Low-Latency NoC Router Architecture for FPGA Computing Systems , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[15]  Stamatis Vassiliadis,et al.  FLUX interconnection networks on demand , 2007, J. Syst. Archit..

[16]  J. Rose,et al.  Mapping multiplexers onto hard multipliers in FPGAs , 2005, The 3rd International IEEE-NEWCAS Conference, 2005..

[17]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[18]  Giorgos Dimitrakopoulos,et al.  Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Gordon J. Brebner,et al.  Networking on chip with platform FPGAs , 2003, Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798).

[20]  Paul Metzgen,et al.  Multiplexer restructuring for FPGA implementation cost reduction , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[21]  Simon W. Moore,et al.  Low-latency virtual-channel routers for on-chip networks , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[22]  Jason Lee,et al.  Predicting the performance of application-specific NoCs implemented on FPGAs , 2010, FPGA '10.

[23]  Nachiket Kapre,et al.  Packet Switched vs. Time Multiplexed FPGA Overlay Networks , 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[24]  Federico Silla,et al.  A comparative study of arbitration algorithms for the Alpha 21364 pipelined router , 2002, ASPLOS X.

[25]  Lesley Shannon,et al.  Routability of Network Topologies in FPGAs , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.