On the Complexity of Three-Dimensional Channel Routing (Extended Abstract)

The 3-D channel routing is a fundamental problem on the physical design of 3-D integrated circuits. The 3-D channel is a 3-D grid G and the terminals are vertices of G located in the top and bottom layers. A net is a set of terminals to be connected. The objective of the 3-D channel routing problem is to connect the terminals in each net with a Steiner tree (wire) in G using as few layers as possible and as short wires as possible in such a way that wires for distinct nets are disjoint. This paper shows that the problem is intractable.

[1]  David S. Johnson,et al.  The NP-Completeness Column: An Ongoing Guide , 1982, J. Algorithms.

[2]  Richard M. Wilson,et al.  Graph puzzles, homotopy, and the alternating group☆ , 1974 .

[3]  Satoshi Tayu,et al.  On the three-dimensional channel routing , 2004, 2005 IEEE International Symposium on Circuits and Systems.

[4]  D A N I E L R A T N E R A N D M A N F R E D W A R M,et al.  The ( n 2-1 )-Puzzle and Related Relocation Problems , 2008 .

[5]  Martin L. Brady,et al.  The three-dimensional channel Routing Problem , 1993, Algorithmic Aspects of VLSI Layout.

[6]  Richard J. Enbody,et al.  Routing the 3-D chip , 1991, 28th ACM/IEEE Design Automation Conference.

[7]  Manfred K. Warmuth,et al.  NxN Puzzle and Related Relocation Problem , 1990, J. Symb. Comput..

[8]  Rolf H. Möhring,et al.  Chapter 8 VLSI network design , 1995 .

[9]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[10]  Alan Siegel,et al.  Optimal wiring between rectangles , 1981, STOC '81.

[11]  Paul G. Spirakis,et al.  Coordinating Pebble Motion on Graphs, the Diameter of Permutation Groups, and Applications , 2015, FOCS.

[12]  Thomas G. Szymanski.  Dogleg Channel Routing is NP-Complete , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  J. Baliga.  Chips go vertical [3D IC interconnection] , 2004, IEEE Spectrum.

[14]  Samuel Loyd,et al.  Mathematical Puzzles of Sam Loyd , 1959 .

[15]  Ted H. Szymanski,et al.  Gravity: Fast placement for 3-D VLSI , 2003, TODE.

[16]  Nisha Checka,et al.  Technology, performance, and computer-aided design of three-dimensional integrated circuits , 2004, ISPD '04.

[17]  Chuan-lin Wu,et al.  Routing in a Three-Dimensional Chip , 1995, IEEE Trans. Computers.