Design of an Energy Efficient 4-2 Compressor

In this paper an energy efficient 4-2 compressor is designed by utilizing only 36 transistors. The architecture of this new compressor consists of 8 transistors (8T) Exclusive-OR-Exclusive-NOR (XOR-XNOR) module and multiplexer based on transmission gate logic. The 8T XOR-XNOR module not only offers high speed, full voltage swing at outputs but also consumes less power. Simulations are done by using Cadence Virtuoso Tool in 180nm CMOS technology. The performance parameters, viz. maximum output delay, average power dissipation and power-delay-product (PDP) are varied from 920.1ps to 211.4ps, 11.85µW to 123.4µW and 10.90fJ to 26.09fJ respectively with a variation of supply voltage from 1V to 3V. Further a comparison of the performance parameters of the proposed compressor is performed with a number of the existing 4-2 compressors at 1.8V supply. Simulation results depict that the proposed compressor attains improvement in terms of speed, power and PDP.

[1]  A. Inoue,et al.  A 4.1 ns compact 54/spl times/54 b multiplier utilizing sign select Booth encoders , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[2]  Kiat Seng Yeo,et al.  Low-power circuit implementation for partial-product addition using pass-transistor logic , 1999 .

[3]  S. Borkar,et al.  A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[4]  Manoj Kumar,et al.  4-2 Compressor Design with New XOR-XNOR Module , 2014, 2014 Fourth International Conference on Advanced Computing & Communication Technologies.

[5]  N. Yoshikawa,et al.  20-GHz 8 $\times$ 8-bit Parallel Carry-Save Pipelined RSFQ Multiplier , 2013, IEEE Transactions on Applied Superconductivity.

[6]  Graham A. Jullien,et al.  On the use of 4:2 compressors for partial product reduction , 2003, CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436).

[7]  Lingamneni Avinash,et al.  Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[8]  Chip-Hong Chang,et al.  Ultra low voltage, low power 4-2 compressor for high speed multiplications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[9]  Gerald E. Sobelman,et al.  New low-voltage circuits for XOR and XNOR , 1997, Proceedings IEEE SOUTHEASTCON '97. 'Engineering the New Century'.

[10]  R. Reis,et al.  Low power 3–2 and 4–2 adder compressors implemented using ASTRAN , 2012, 2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS).

[11]  Chip-Hong Chang,et al.  Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Vinay Kumar,et al.  Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  M. Nagamatsu,et al.  A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology , 1991 .

[14]  Ravi Nirlakalla,et al.  Performance evaluation of high speed compressors for high speed multipliers , 2011 .

[15]  K.K. Parhi,et al.  Low-power 4-2 and 5-2 compressors , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).