A software performance simulation methodology for rapid system architecture exploration

The performance simulation of embedded system designs is often a time consuming process. Whereas the simulation performance of hardware models depends on the chosen abstraction level, the software part is usually simulated with a slow instruction-set-simulator (ISS), which greatly limits the entire simulation speed. In this paper we solve this problem by presenting a highly automated methodology developed in the SIMBA project, which replaces the ISS simulation with a faster performance simulation of a delay-annotated software model suitable for architecture exploration of embedded systems. We use the assembler code from the target cross-compiler and the processor datasheet to automatically generate a SystemC model, which consists of the original software code annotated with additional delay information for each C-code statement to consider the timing behavior of the software. This also encompasses micro-architectural effects like different cache/memory access times and pipeline effects. The SystemC simulation of the model provides accurate information on the timing behavior of the software close to the software execution time on the target processor. We use a sample software C-code to prove our methodology and compare it with an ISS simulation. It shows that our methodology provides a several times faster performance simulation of the software with sufficient accuracy regarding timing, cache, pipeline and memory accesses as it is required for the architecture exploration of embedded systems.