Area efficient vlsi architectures for image computations

In this dissertation, several VLSI architectures which support computational requirements arising in real-time image compression are proposed. These solutions lead to area efficient and/or faster designs, compared with known designs in the literature. The problems studied include computing discrete Fourier transform, arithmetic Fourier transform, vector quantization (VQ), and Huffman coding. These problems arise frequently in image compression as well as in other image processing applications. For computing the DFT, two different designs are proposed based on the reconfigurable mesh, and linear arrays connected by shuffle network. On an $N\log N$ x $N\log N$ bit model of the reconfigurable mesh, $O(1)$ time algorithm for computing the N-point DFT is shown. This leads to an $AT\sp2$ optimal design. Using linear arrays connected by shuffle network, a class of $AT\sp2$ optimal architectures for computing the DFT is derived, where $T\in\lbrack\log N, \sqrt{N\log N}\rbrack$ and $A=N\sp2\log\sp2 N/T\sp2$. In addition, this is a processor-time optimal design in the entire range of $T\in\lbrack\log N, \sqrt{N\log N}\rbrack .$ Using linear arrays, a fast algorithm for computing the arithmetic Fourier transform which is a simplified approach for computing the Fourier coefficients is shown. It requires $O(p)$ adders and a multiplier to compute N-point Fourier coefficients. This solution leads to processor-time optimal designs, where $1\le p\le N$. Based on our techniques on the reconfigurable mesh, $O(1)$ time solutions to several arithmetic operations such as multiplication and division are shown in the bit model of VLSI. A new tree search algorithm for performing VQ is shown. Compared with known tree search algorithms which require $O(k\log N)$ multiplications and $O(\log N)$ PEs for an N codevectors and a k-dimensional input vector, our algorithm requires $O(\log N)$ comparisons. The proposed algorithm does not require any multiplication, and employs $O(N)$ storage to store the hyperplanes used in the search. It can support high data rate compression of video signals. Compared with known PE designs employing tree search, the proposed architecture requires significantly less area. In the last section, we show an area efficient design for Huffman coding. Compared with earlier designs which require $O(N\sp2)$ PEs for coding $(\log N)$-bit symbols, our design achieves a throughput of 40Mbps for coding 8-bit symbols using a single PE. It can support real-time coding of data arising in current and proposed MPEG rates. The estimated die size is 3.5 x 3.5$mm\sp2$ using 1.2$\mu$ technology. An attractive feature of this design is the flexibility of the design: different Huffman trees can be employed by altering the contents of storage without altering the data path within the PE. (Copies available exclusively from Micrographics Department, Doheny Library, USC, Los Angeles, CA 90089-0182.)