Digital FIR filter architecture based on the residue number system

In this paper, architecture of residue number system used in FIR filters, is presented. For many years residue number coding has been recognized as a system which provides capability for implementation of a high speed addition and multiplication. These advantages of residue number system coding for the high speed FIR filters design results from the fact that an digital FIR filter requires only addition and multiplication. The proposed FIR filter architecture is performed as series of modulo multiplication and accumulation across each modulo. A numerical example illustrates the principles of FIR filtering of an 32 order low pass filter. This architecture is compared with FIR filters direct synthesis. .

[1]  Hong Shen,et al.  Adder based residue to binary number converters for (2n-1, 2n, 2n+1) , 2002, IEEE Trans. Signal Process..

[2]  W. Kenneth Jenkins,et al.  The use of residue number systems in the design of finite impulse response digital filters , 1977 .

[3]  W. Freking,et al.  Low-power FIR digital filters using residue arithmetic , 1997, Conference Record of the Thirty-First Asilomar Conference on Signals, Systems and Computers (Cat. No.97CB36136).

[4]  John G. Proakis,et al.  Digital Signal Processing Using MATLAB , 1999 .

[5]  S. Piestrak.  A high-speed realization of a residue to binary number system converter , 1995 .

[6]  G. Cardarilli,et al.  Reducing power dissipation in complex digital filters by using the quadratic residue number system , 2000, Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154).

[7]  Keivan Navi,et al.  New Arithmetic Residue to Binary Converters , 2007 .

[8]  Keivan Navi,et al.  A new high dynamic range moduli set with efficient reverse converter , 2008, Comput. Math. Appl..

[9]  Mi Lu,et al.  A Novel Division Algorithm for the Residue Number System , 1992, IEEE Trans. Computers.

[10]  Wei Wang,et al.  A note on "A high-speed residue-to-binary converter for three-moduli (2/sup k/ 2/sup k/ - 1, 2/sup k-1/ - 1) RNS and a scheme for its VLSI implementation" , 2000 .

[11]  H. Garner.  The residue number system , 1959, IRE-AIEE-ACM '59 (Western).

[12]  Mahesh Mehendale,et al.  Low power realization of residue number system based FIR filters , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[13]  Michael A. Soderstrand,et al.  Residue number system arithmetic: modern applications in digital signal processing , 1986 .

[14]  I. Flores.  Residue Arithmetic and Its Application to Computer Technology (Nicholas S. Szabo and Richard I. Tanaka) , 1969 .

[15]  Kenneth H. Rosen.  Elementary Number Theory , 2004 .

[16]  A. Hiasat,et al.  Residue-to-binary arithmetic converter for the moduli set (2/sup k/, 2/sup k/-1, 2/sup k-1/-1) , 1998 .

[17]  F. Pourbigharaz,et al.  A Signed-Digit Architecture for Residue to Binary Transformation , 1997, IEEE Trans. Computers.

[18]  Gian Carlo Cardarilli,et al.  Low-power implementation of polyphase filters in Quadratic Residue Number system , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[19]  Tadeusz Tomczak,et al.  Fast Sign Detection for RNS $(2^{n}-1,2^{n},2^{n}+1)$ , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[20]  Donald Ervin Knuth,et al.  The Art of Computer Programming , 1968 .

[21]  Sebastiano Impedovo,et al.  A New Technique for Fast Number Comparison in the Residue Number System , 1993, IEEE Trans. Computers.

[22]  F. Petry,et al.  The digit parallel method for fast RNS to weighted number system conversion for specific moduli (2/sup k/-1,2/sup k/,2/sup k/+1) , 1997 .