Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30 fr/s for CIF-video

We have developed a media processor core for MPEG4/H.26X codec LSI, which realizes a real-time bi-directional encoding/decoding for CIF-resolution video at the frame rate of 30 fr/s. The core processor contains 6.3 M-transistors on only 14 mm silicon area and consumes 280 mW at 1.8 V. It features an MPEG-oriented hybrid architecture which incorporates a SIMD processor optimized for matrix-operation, a programmable VLC engine and two-dimensional multifunction DMA. Another features are a memory reduction approach by hardware assist and an operand isolation scheme, which realizes low cost and low power characteristics, respectively.

[1]  Tsuyoshi Nakamura,et al.  A MPEG4 programmable codec DSP with an embedded pre/post-processing engine , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[2]  H. Momose,et al.  A 60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[3]  A. Tournier,et al.  A single-chip CIF 30 Hz H261, H263, and H263+ video encoder/decoder with embedded display controller , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[4]  Gert Slavenburg,et al.  An architectural overview of the programmable multimedia processor, TM-1 , 1996, COMPCON '96. Technologies for the Information Superhighway Digest of Papers.