Design of a high speed parallel encoder for convolutional codes

Abstract This paper presents the design of high speed parallel architectures for convolutional encoders and its implementation on FPGA devices. Convolutional codes are widely used in telecommunication applications to improve the data transmission reliability over noisy chanels. The architecture proposed here combines parallel and pipelining techniques. A purely parallel approach can increase the number of processed bits per clock cycle. Unfortunately, the critical path propagation delay increases with the parallelism level. Consequently, the operating clock frequency decreases which in turn can dramatically limit the benefit of parallelization. This drawback can be significantly reduced using pipelining techniques. As a result, the critical path depends no more on the parallelism level. The encoder architectures have been implemented on FPGA devices of the Altera Flex10KE family. Bit rates up to 6.61 Gbits/s have been achieved on 32-bit parallel implementations.

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