Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques

Due to the increased speed in modern designs, testing for delay faults has become an important issue in the post-production test of manufactured chips. A high fault coverage is needed to guarantee the correct temporal behavior. Today's ATPG algorithms have difficulties to reach the desired fault coverage due to the high complexity of modern designs. In this paper, we describe how to efficiently integrate the reuse of learned information into state-of-the-art SAT-based ATPG algorithms and, by this, reduce the number of unclassified faults significantly. For further reduction, a post-classification phase is presented. Experimental results for ATPG for delay faults on large industrial circuits show the robustness and feasibility of the approach.

[1]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[2]  Dhiraj K. Pradhan,et al.  Accelerated dynamic learning for test pattern generation in combinational circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Eugene Goldberg,et al.  BerkMin: A Fast and Robust Sat-Solver , 2002 .

[4]  Niklas Sörensson,et al.  An Extensible SAT-solver , 2003, SAT.

[5]  Rolf Drechsler,et al.  Reusing Learned Information in SAT-based ATPG , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[6]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[7]  Rolf Drechsler,et al.  Experimental Studies on SAT-Based ATPG for Gate Delay Faults , 2007, 37th International Symposium on Multiple-Valued Logic (ISMVL'07).

[8]  Michael S. Hsiao,et al.  Integration of learning techniques into Incremental Satisfiability for efficient path-delay fault test generation , 2005, Design, Automation and Test in Europe.

[9]  Eric Lindbloom,et al.  Transition Fault Simulation , 1987, IEEE Design & Test of Computers.

[10]  J. P. Marques,et al.  GRASP : A Search Algorithm for Propositional Satisfiability , 1999 .

[11]  Hideo Fujiwara,et al.  SPIRIT: a highly robust combinational test generation algorithm , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[12]  Rolf Drechsler,et al.  Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults , 2007, 2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007).

[13]  Sharad Malik,et al.  Efficient conflict driven learning in a Boolean satisfiability solver , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[14]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[15]  Kwang-Ting Cheng,et al.  Delay fault testing for VLSI circuits , 1998 .

[16]  Joonyoung Kim,et al.  SATIRE: A new incremental satisfiability engine , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[17]  Tracy Larrabee,et al.  Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Rolf Drechsler,et al.  On Acceleration of SAT-Based ATPG for Industrial Designs , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Robert K. Brayton,et al.  Combinational test generation using satisfiability , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Joao Marques-Silva,et al.  Robust search algorithms for test pattern generation , 1997, Proceedings of IEEE 27th International Symposium on Fault Tolerant Computing.