Design and implementation of a novel Boundary-Scan circuit in an SOI-Based FPGA

A novel Boundary-Scan circuit compatible with IEEE 1149.1 standard and designed for our SOI-Based FPGA is presented in this paper. The new Boundary-Scan circuit serves the test of FPGA at the chip as well as board level and the added features facilitate the configuration and verification functions of FPGA. The Boundary-Scan circuit in this paper has been implemented in an SRAM-Based FPGA fabricated by a 0.5µm SOI-CMOS process. The test results from the fabricated chip demonstrate that this circuit successfully realizes the desired functions in programming, verification and testing.