Multibranch Inductance Extraction Procedure for Multichip Power Modules

This article presents a measurement-based technique for estimating the parasitic inductances associated with the interconnection structures of a multichip power module (MCPM) at a finer granularity than has been previously demonstrated. The technique introduced here makes it possible to determine an estimate of the interconnect inductances at each individual die position within the module geometry. For this purpose, this technique leverages the measured input impedance of an MCPM in the frequency domain, which has been carefully shaped by employing discrete capacitors in place of a semiconductor die. An example of the proposed technique is provided for an MCPM with four die positions per switch position. The provided theoretical formulation is verified by its application to a physical test subject, which is designed to represent a generic MCPM. Owing to the efficiency of this extraction technique and the possibility of providing direct empirical validation for FEA-obtained estimates, the proposed approach is expected to be of particular interest to MCPM designers for use in design optimization.

[1]  C. Paul,et al.  Inductance calculations using partial inductances and macromodels , 1995, Proceedings of International Symposium on Electromagnetic Compatibility.

[2]  Dushan Boroyevich,et al.  Modeling and simulation of 2 kV 50 A SiC MOSFET/JBS power modules , 2009, 2009 13th European Conference on Power Electronics and Applications.

[3]  Li Yang,et al.  Estimation and minimization of power loop inductance in 135 kW SiC traction inverter , 2018, 2018 IEEE Applied Power Electronics Conference and Exposition (APEC).

[4]  Eckart Hoene,et al.  Investigation and PEEC based simulation of radiated emissions produced by power electronic converters , 2010, 2010 6th International Conference on Integrated Power Electronics Systems.

[5]  Yehea I. Ismail,et al.  Modeling skin and proximity effects with reduced realizable RL circuits , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Liyu Yang,et al.  Measurement-Based Method to Characterize Parasitic Parameters of the Integrated Power Electronics Modules , 2007, IEEE Transactions on Power Electronics.

[7]  Hans-Peter Nee,et al.  Analysis of parasitic elements of SiC power modules with special emphasis on reliability issues , 2016, 2016 IEEE Applied Power Electronics Conference and Exposition (APEC).

[8]  G. Wachutka,et al.  Modeling of parasitic inductive effects in power modules , 1997, Proceedings of 9th International Symposium on Power Semiconductor Devices and IC's.

[9]  Z. John Shen,et al.  A New Characterization Technique for Extracting Parasitic Inductances of SiC Power MOSFETs in Discrete and Module Packages Based on Two-Port S-Parameters Measurement , 2018, IEEE Transactions on Power Electronics.

[10]  Lionel Pichon,et al.  Detection of Defects in Wiring Networks Using Time Domain Reflectometry , 2010, IEEE Transactions on Magnetics.

[11]  A. Lemmon,et al.  Parasitic extraction procedure for silicon carbide power modules , 2015, 2015 IEEE International Workshop on Integrated Power Packaging (IWIPP).

[13]  Jih-Sheng Lai,et al.  Characterization of power electronics system interconnect parasitics using time domain reflectometry , 1998 .

[14]  D. Cottet,et al.  Numerical Simulations for Electromagnetic Power Module Design , 2006, 2006 IEEE International Symposium on Power Semiconductor Devices and IC's.

[15]  Shijie Wang.  Electrical Design Considerations and Packaging of Power Electronic Modules , 2013 .

[16]  Enrico Santi,et al.  Parasitic modeling for accurate inductive switching simulation of converters using SiC devices , 2013, 2013 IEEE Energy Conversion Congress and Exposition.

[18]  Clayton R. Paul,et al.  The Concept of Loop Inductance , 2010 .