De-elastisation: From asynchronous dataflows to synchronous circuits

Asynchronous VLSI programming provides a flexible abstract formalism for concurrent systems but the is an issue for industrial adoption. The asynchronous design paradigm provides `elasticity' enabling the system to tolerate delays in communication and computation but can impose a prohibitive communication overhead when applied at a fine-grained level. This paper proposes `De-elastisation' in a CAD flow for asynchronous dataflow networks to improve the circuits' performance and area. To preserve the architectural advantages of asynchronous design (e.g. short cycles), circuits are classified into blocking and non-blocking loops which the De-elastisation scheme relies upon. The technique is incorporated in the Teak CAD flow. Experimental results on substantial case studies show significant performance and area improvements. This work shows 3× improvement for the first category of circuits, suitable for iterative realisations and DSP-like architectures and 4× for the second category which are suitable for concurrent realisations.

[1]  Wei Shi,et al.  Critical path analysis in data-driven asynchronous pipelines , 2012, 2012 International Conference on Computer Communication and Informatics.

[2]  S.C. Goldstein,et al.  Leveraging Protocol Knowledge in Slack Matching , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[3]  Jean-Michel Chabloz,et al.  Globally-Ratiochronous, Locally-Synchronous Systems , 2012 .

[4]  Peter A. Beerel,et al.  Performance Analysis of Asynchronous Circuits Using Markov Chains , 2002, Concurrency and Hardware Design.

[5]  Navaneeth Jamadagni,et al.  An Asynchronous Divider Implementation , 2012, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems.

[6]  Elizabeth Latronico,et al.  System Design, Modeling, and Simulation Using Ptolemy Ii Ontologies , 2013 .

[7]  Luciano Lavagno,et al.  Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Josep Carmona,et al.  Elastic Circuits , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Daniel Marcos Chapiro,et al.  Globally-asynchronous locally-synchronous systems , 1985 .

[10]  Peter A. Beerel,et al.  Slack matching mode-based asynchronous circuits for average-case performance , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[11]  Doug A. Edwards,et al.  Asynchronous Data-Driven Circuit Synthesis , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Peter A. Beerel,et al.  Performance-Driven Clustering of Asynchronous Circuits , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Yehea I. Ismail,et al.  Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation , 2013, 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems.

[14]  Doug A. Edwards,et al.  Attacking control overhead to improve synthesised asynchronous circuit performance , 2005, 2005 International Conference on Computer Design.

[15]  Shirshendu Das,et al.  A formal framework for interfacing mixed-timing systems , 2013, Integr..

[16]  Alberto L. Sangiovanni-Vincentelli,et al.  Theory of latency-insensitive design , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  George Michelogiannakis,et al.  Elastic-buffer flow control for on-chip networks , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[18]  Peter A. Beerel,et al.  Slack matching asynchronous designs , 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).

[19]  Forrest Brewer,et al.  Synthesizing Synchronous Elastic Flow Networks , 2008, 2008 Design, Automation and Test in Europe.

[20]  Doug A. Edwards,et al.  Teak: A Token-Flow Implementation for the Balsa Language , 2009, 2009 Ninth International Conference on Application of Concurrency to System Design.

[21]  Doug A. Edwards,et al.  Balsa: An Asynchronous Hardware Synthesis Language , 2002, Comput. J..

[22]  Doug A. Edwards,et al.  Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA , 2014, 2014 17th Euromicro Conference on Digital System Design.

[23]  Steven M. Nowick,et al.  Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems , 2002, DAC '02.

[24]  Jordi Cortadella,et al.  Speculation in Elastic Systems , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[25]  Kenneth S. Stevens,et al.  Design of low energy, high performance synchronous and asynchronous 64-point FFT , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[26]  Jens Sparsø,et al.  A Behavioral Synthesis Frontend to the Haste/TiDE Design Flow , 2009, 2009 15th IEEE Symposium on Asynchronous Circuits and Systems.

[27]  Mahdi Jelodari Mamaghani,et al.  eTeak: A Data-driven Synchronous Elastic Synthesiser , 2013, ACSD 2013.

[28]  Alexandre Yakovlev,et al.  Improved Parallel Composition of Labelled Petri Nets , 2011, 2011 Eleventh International Conference on Application of Concurrency to System Design.

[29]  Vishal Gupta,et al.  Performance estimation and slack matching for pipelined asynchronous architectures with choice , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[30]  Karl Papadantonakis,et al.  The Lutonium: a sub-nanojoule asynchronous 8051 microcontroller , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..