Technology of FinFET for High RF and Analog/Mixed-Signal Performance Circuits

In this paper, we discuss the process, layout and device technologies of FinFET to obtain high RF and analog/mixed-signal performance circuits. The fin patterning due to Side-wall transfer (SWT) technique is useful to not only fabricate narrow fin line but also suppress the fin width variation comparing with ArF and EB lithography. The H2 annealing after Si etching is useful for not only to improve the mobility of electron and hole but also to reduce flicker noise of FinFET. The noise decreases as the scaling of fin width and that of FinFET with below 50 nm fin width is satisfied with the requirement from 25 nm technology node in ITRS roadmap 2013. This lower noise is attributed to the decrease of electric field from the channel to the gate electrode. Additionally, the optimum layout of FinFET is discussed for RF performance. In order to obtain higher fT and fmax, it is necessary to have the optimized finger length and reduced capacitances between the gate and Si substrate and between gate and source, drain contact region. According to our estimation, the fT of FinFET with the optimized layout should be lower than that of planar MOSFET when the gate length is longer than 10 nm due to larger gate capacitance. In conclusion, FinFET is suitable for high performance digital and analog/mixed-signal circuits. On the other hand, planar MOSFET is better rather than FinFET for RF circuits. key words: FinFET, analog, RF, flicker noise, fT , fmax

[1]  Shirai,et al.  Evidence of spontaneous formation of steps on silicon (100). , 1996, Physical review. B, Condensed matter.

[2]  B. Yang,et al.  FinFET performance advantage at 22nm: An AC perspective , 2008, 2008 Symposium on VLSI Technology.

[3]  M. Chan,et al.  Gate resistance modeling of multifin MOS devices , 2006, IEEE Electron Device Letters.

[4]  Chenming Hu,et al.  Sub-20 nm CMOS FinFET technologies , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[5]  J. Bokor,et al.  Hydrogen annealing effect on DC and low-frequency noise characteristics in CMOS FinFETs , 2003, IEEE Electron Device Letters.

[6]  H. T. Lin,et al.  A 16nm FinFET CMOS technology for mobile SoC and computing applications , 2013, 2013 IEEE International Electron Devices Meeting.

[7]  Ching-Te Chuang,et al.  Impacts of single trap induced random telegraph noise on finfet devices and SRAM cell stability , 2011, IEEE 2011 International SOI Conference.

[8]  K. Yahashi,et al.  Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[9]  T. Ohguro,et al.  The optimum device parameters for high RF and analog/MS performance in planar MOSFET and FinFET , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[10]  Mikael Östling,et al.  Low-frequency noise in SiGe channel pMOSFETs on ultra-thin body SOI with Ni-silicided source/drain , 2005 .

[11]  H. Ishiuchi,et al.  FinFET: the prospective multi-gate device for future SoC applications , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

[12]  T. Ohguro,et al.  Analysis of Fin width and temperature dependence of flicker noise for bulk-FinFET , 2009, 2009 European Microwave Integrated Circuits Conference (EuMIC).

[13]  K. Yahashi,et al.  Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[14]  Guido Groeseneken,et al.  Identifying the Bottlenecks to the RF Performance of FinFETs , 2010, 2010 23rd International Conference on VLSI Design.

[15]  J.-P. Raskin,et al.  Optimizing FinFET geometry and parasitics for RF applications , 2008, 2008 IEEE International SOI Conference.

[16]  A. Mercha,et al.  Double-Gate finFETs as a CMOS Technology Downscaling Option: An RF Perspective , 2007, IEEE Transactions on Electron Devices.

[17]  M. Chan,et al.  Parasitic Minimization in RF Multi-Fin FETs , 2005, 2005 IEEE Conference on Electron Devices and Solid-State Circuits.

[18]  N. Collaert,et al.  Low-frequency noise in triple-gate n-channel bulk FinFETs , 2011, 2011 21st International Conference on Noise and Fluctuations.

[19]  J.-P. Raskin,et al.  Dependence of finFET RF performance on fin width , 2006, Digest of Papers. 2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.

[20]  Shien-Yang Wu,et al.  A 16nm FinFET CMOS technology for mobile SoC and computing applications , 2013 .

[21]  Y. Tsunashima,et al.  FinFET Process and Integration Technology for High Performance LSI in 22 nm node and beyond , 2007, 2007 International Workshop on Junction Technology.

[22]  Y. Toyoshima,et al.  Direct evaluation of DC characteristic variability in FinFET SRAM Cell for 32 nm node and beyond , 2007, 2007 IEEE International Electron Devices Meeting.