Transistor size optimization in digital circuits using ant colony optimization for continuous domain

In this paper, ant colony optimization ACO algorithm is presented, as a tool to find transistor sizes in digital circuits. Performance of ACO has been tested on four digital circuits, of different complexity, to find optimum balance between power and delay of circuits. Optimization problem has been set up by first, formulating an objective function, to be minimized, for each circuit and then finding the values of variables of circuits, using optimization algorithm. For the purpose of examining the results, circuits are optimized using genetic algorithm GA also. Results show that, ACO performs better than GA, for all the four circuits, in finding optimized transistor sizes. Copyright © 2012 John Wiley & Sons, Ltd.

[1]  Ali Afzali-Kusha,et al.  Optimizing High Speed Flip-Flop Using Genetic Algorithm , 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

[2]  Massimo Alioto,et al.  Power-delay optimization of D-latch/MUX source coupled logic gates: Research Articles , 2005 .

[3]  Maryam Shojaei Baghini,et al.  Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization , 2009, 2009 22nd International Conference on VLSI Design.

[4]  S. Demir.  Matching circuit design using ant colony optimization method [transmission line impedance matching] , 2003, IEEE Antennas and Propagation Society International Symposium. Digest. Held in conjunction with: USNC/CNC/URSI North American Radio Sci. Meeting (Cat. No.03CH37450).

[5]  Kaushik Roy,et al.  Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI , 2006, 2006 International Conference on Computer Design.

[6]  Thomas Stützle,et al.  Ant Colony Optimization , 2009, EMO.

[7]  Janet Roveda,et al.  Robust gate sizing by Uncertainty Second Order Cone , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

[8]  Thomas Stützle,et al.  Ant colony optimization: artificial ants as a computational intelligence technique , 2006 .

[9]  Kalyanmoy Deb,et al.  An introduction to genetic algorithms , 1999 .

[10]  Andrea Pugliese,et al.  A new efficient SC integrator scheme for high‐speed low‐power applications , 2012, Int. J. Circuit Theory Appl..

[11]  Hubert Kaeslin,et al.  Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits , 1996, PPSN.

[12]  Marco Dorigo,et al.  Ant colony optimization for continuous domains , 2008, Eur. J. Oper. Res..

[14]  Muhammad Murtadha Othman,et al.  Ant Colony Based Optimization Technique for Voltage Stability Control , 2006 .

[15]  Massimo Alioto,et al.  Power-delay optimization of D-latch/MUX source coupled logic gates , 2005, Int. J. Circuit Theory Appl..

[16]  Yin-Tsung Hwang,et al.  A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  Jun Zhang,et al.  Optimization of power electronic circuits using ant colony system , 2008, 2008 IEEE Power Electronics Specialists Conference.

[18]  Sung-Mo Kang,et al.  An exact solution to the transistor sizing problem for CMOS circuits using convex optimization , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Yu Chien-Cheng.  Low-Power Double Edge-Triggered Flip-Flop Circuit Design , 2008, 2008 3rd International Conference on Innovative Computing Information and Control.

[20]  Yu Chien-Cheng.  Design of Low-Power Double Edge-Triggered Flip-Flop Circuit , 2007, 2007 2nd IEEE Conference on Industrial Electronics and Applications.

[21]  Alireza Rezaee,et al.  Power optimization in 70nm technology , 2010, 2010 2nd International Conference on Computer Engineering and Technology.

[22]  Ngai Wong,et al.  Analog circuit design by nonconvex polynomial optimization: Two design examples , 2010 .