CAS-FEST 2010: Mitigating Variability in Near-Threshold Computing

Near threshold computing has recently gained significant interest due to its potential to address the prohibitive increase of power consumption in a wide spectrum of modern VLSI circuits. This tutorial paper starts by reviewing the benefits and challenges of near threshold computing. We focus on the challenge of variability and discuss circuit and architecture solutions tailored to three different circuit fabrics: logic, memory, and clock distribution. Soft-edge clocking, body-biasing, mismatch-tolerant memories, asynchronous operation and low-skew clock networks are presented to mitigate variability in the near threshold VDD regime.

[1]  David Blaauw,et al.  Theoretical and practical limits of dynamic voltage scaling , 2004, Proceedings. 41st Design Automation Conference, 2004..

[2]  A. Chandrakasan,et al.  A 180mV FFT processor using subthreshold circuit techniques , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[3]  Bo Zhai,et al.  Performance and Variability Optimization Strategies in a Sub-200mV, 3.5pJ/inst, 11nW Subthreshold Processor , 2007, 2007 IEEE Symposium on VLSI Circuits.

[4]  Kaushik Roy,et al.  ABRM: Adaptive $ \beta$-Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  A.P. Chandrakasan,et al.  A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.

[6]  Naveen Verma,et al.  A 65nm Sub-Vt Microcontroller with Integrated SRAM and Switched-Capacitor DC-DC Converter , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[7]  Jie Gu,et al.  A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  David Blaauw,et al.  Crosshairs SRAM — An adaptive memory for mitigating parametric failures , 2010, 2010 Proceedings of ESSCIRC.

[9]  David Blaauw,et al.  Clock network design for ultra-low power applications , 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

[10]  David Blaauw,et al.  Yield-Driven Near-Threshold SRAM Design , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  David Blaauw,et al.  Timing yield enhancement through soft edge flip-flop based design , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[12]  C.H. Kim,et al.  A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V$_{\min}$ Lowering Techniques and Deep Sleep Mode , 2008, IEEE Journal of Solid-State Circuits.

[13]  Marcel J. M. Pelgrom,et al.  Transistor matching in analog CMOS applications , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[14]  Uri C. Weiser,et al.  Interconnect-power dissipation in a microprocessor , 2004, SLIP '04.

[15]  Seok-Jun Lee,et al.  Microwatt Embedded Processor Platform for Medical System-on-Chip Applications , 2011, IEEE Journal of Solid-State Circuits.

[16]  Anantha Chandrakasan,et al.  Characterizing and modeling minimum energy operation for subthreshold circuits , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[17]  Kaushik Roy,et al.  REad/access-preferred (REAP) SRAM - architecture-aware bit cell design for improved yield and lower VMIN , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[18]  R. M. Swanson,et al.  Ion-implanted complementary MOS transistors in low-voltage circuits , 1972 .

[19]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[20]  Jan M. Rabaey,et al.  Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation , 2008, ISQED 2008.

[21]  C.H. Kim,et al.  A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing , 2008, IEEE Journal of Solid-State Circuits.

[22]  A.P. Chandrakasan,et al.  A 65 nm Sub-$V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter , 2008, IEEE Journal of Solid-State Circuits.

[23]  Kaushik Roy,et al.  A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[24]  Leland Chang,et al.  A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS , 2007, 2007 IEEE Symposium on VLSI Circuits.

[25]  David Blaauw,et al.  Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits , 2010, Proceedings of the IEEE.

[26]  Daeyeon Kim,et al.  The Phoenix Processor: A 30pW platform for sensor applications , 2008, 2008 IEEE Symposium on VLSI Circuits.

[27]  Rajalakshmi Srinivasaraghavan.  IBM PowerPC , 2011, Encyclopedia of Parallel Computing.

[28]  Kaushik Roy,et al.  A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).