A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme

A 5-Gb/s/pin transceiver for DDR memory interface is proposed with a crosstalk suppression scheme. The proposed transceiver implements a staggered memory bus topology and a glitch canceller to suppress crosstalk-induced distortions in a memory channel. The transceiver is implemented using 0.18 mum CMOS process and operates at 5 Gb/s. The results demonstrate widened eye diagram and lower bit error rate. The eye width and height of the proposed scheme increases 28.3% and 11.1% compared to the conventional memory transceiver, respectively. The peak-to-peak jitter of output data is 52.82 ps.

[1]  Jeffrey A. Andrews,et al.  Xbox 360 system architecture , 2005 .

[2]  Brian Young.  Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages , 2000 .

[3]  Woo-Jin Lee,et al.  An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion , 2008, IEEE Journal of Solid-State Circuits.

[4]  Young-Hyun Jun,et al.  An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[5]  C.W. Werner,et al.  A 2 Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[6]  S. Chandramouli,et al.  Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits , 2004, IEEE Journal of Solid-State Circuits.

[7]  Kaushik Roy,et al.  A twisted-bundle layout structure for minimizing inductive coupling noise , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[8]  Young Sik Hur,et al.  Equalization and near-end crosstalk (NEXT) noise cancellation for 20-Gb/s 4-PAM backplane serial I/O interconnections , 2005, IEEE Transactions on Microwave Theory and Techniques.

[9]  Yu Cao,et al.  Effects of global interconnect optimizations on performance estimation of deep submicron design , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[10]  A. Hajimiri,et al.  Cancellation of crosstalk-induced jitter , 2006, IEEE Journal of Solid-State Circuits.

[11]  Young-Hyun Jun,et al.  A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[12]  Kinam Kim,et al.  Low-jitter multi-phase digital DLL with closest edge selection scheme for DDR memory interface , 2008 .

[13]  Lei He,et al.  Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization , 2000, ISPD '00.