Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics
暂无分享,去创建一个
[1] Yu Cao,et al. Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] Michael Snyder,et al. A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect , 1999 .
[3] A. Gattiker,et al. Timing yield estimation from static timing analysis , 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.
[4] Duane S. Boning,et al. SPATIAL VARIATION IN SEMICONDUCTOR PROCESSES: MODELING FOR CONTROL , 1998 .
[5] S. Fischer,et al. A 600 MHz IA-32 microprocessor with enhanced data streaming for graphics and video , 1999 .
[6] Sani R. Nassif,et al. A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance , 2000, Proceedings 37th Design Automation Conference.
[7] W. Dai,et al. Timing analysis taking into account interconnect process variation , 2001, 2001 6th International Workshop on Statistical Methodology (Cat. No.01TH8550).
[8] Lawrence T. Pileggi,et al. Calculating worst-case gate delays due to dominant capacitance coupling , 1997, DAC.
[9] Yu Cao,et al. Accurate in situ measurement of peak noise and delay change induced by interconnect coupling , 2001 .
[10] Malgorzata Marek-Sadowska,et al. Incremental delay change due to crosstalk noise , 2002, ISPD '02.
[11] Duane S. Boning,et al. Statistical metrology: understanding spatial variation in semiconductor manufacturing , 1996, Advanced Lithography.
[12] Sani R. Nassif. Design for Variability in DSM Technologies , 2000 .
[13] D. Boning,et al. Statistical metrology - measurement and modeling of variation for advanced process development and design rule generation , 1998 .