Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions
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[1] Imed Moussa,et al. An integrated design and verification methodology for reconfigurable multimedia systems , 2005, Design, Automation and Test in Europe.
[2] Kwang-Ting Cheng,et al. Automatic generation of functional vectors using the extended finite state machine model , 1996, TODE.
[3] Rolf Drechsler,et al. Gatecomp: Equivalence Checking of Digital Circuits in an Industrial Environment , 2002 .
[4] Masahiro Fujita,et al. Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths , 2005, TODE.
[5] Franco Fummi,et al. Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation , 2008, 2008 Design, Automation and Test in Europe.
[6] Daniel D. Gajski,et al. Essential Issues in Codesign , 1997 .
[7] Joao Marques-Silva,et al. Towards Equivalence Checking Between TLM and RTL Models , 2007, 2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007).
[8] Daniel Gajski,et al. Transaction level modeling: an overview , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).
[9] Carl-Johan H. Seger,et al. An industrially effective environment for formal hardware verification , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[10] Alan Mishchenko,et al. Scalable and scalably-verifiable sequential synthesis , 2008, ICCAD 2008.
[11] J.R. Burch,et al. Robust latch mapping for combinational equivalence checking , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[12] Robert K. Brayton,et al. Combinational techniques for sequential equivalence checking , 2010, Formal Methods in Computer Aided Design.
[13] Rolf Drechsler,et al. System level validation using formal techniques , 2005 .
[14] Leslie Lamport,et al. Time, clocks, and the ordering of events in a distributed system , 1978, CACM.
[15] Nikhil Sharma,et al. Non-cycle-accurate Sequential Equivalence Checking , 2009, 2009 46th ACM/IEEE Design Automation Conference.
[16] Yuan Lu,et al. Embedded tutorial: formal equivalence checking between system-level models and RTL , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[17] Robert F. Damiano,et al. A practical and efficient method for compare-point matching , 2002, DAC '02.
[18] Jacob A. Abraham,et al. Automatic decomposition for sequential equivalence checking of system level and RTL descriptions , 2006, Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings..
[19] Daniel Kroening,et al. Checking consistency of C and Verilog using predicate abstraction and induction , 2004, ICCAD 2004.
[20] Roberto Passerone,et al. Specification, Synthesis, and Simulation of Transactor Processes , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[21] Wolfgang Ecker,et al. Execution semantics and formalisms for multi-abstraction TLM assertions , 2006, Fourth ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2006. MEMOCODE '06. Proceedings..
[22] F. Fummi,et al. EFSM Manipulation to Increase High-Level ATPG , 2006 .