Temperature Dependence of Subthreshold Characteristics of Negative Capacitance Recessed-Source/Drain (NC R-S/D) SOI MOSFET

This paper presents the subthreshold performance analysis of negative capacitance Recessed-Source/Drain SOI MOSFET (NC R-S/D SOI MOSFET). The effect of ferroelectric thickness on the subthreshold performance of NC R-S/D SOI MOSFET at given R-S/D thickness is studied and the same is compared with negative capacitance SOI MOSFET (NC SOI MOSFET). Device performance is also assessed at two different temperatures 300K and 340K to observe the device behavior at high temperatures. The parameters such as transfer characteristics, variation in subthreshold swing (SS) with drain current, the effect of ferroelectric thickness on the minimum subthreshold swing and the influence of negative capacitance on gate capacitance of the device are studied. The minimum subthreshold swing of 29mV/decade is achieved for NC R-S/D SOI MOSFET at 300K with a ferroelectric thickness of 5.5nm and recessed source/drain thickness of 10nm which is much lower than Boltzmann's limit (60mV/decade).

[1]  Chenming Hu,et al.  Ultrathin-body SOI MOSFET for deep-sub-tenth micron era , 2000, IEEE Electron Device Letters.

[2]  Thomas Mikolajick,et al.  Incipient Ferroelectricity in Al‐Doped HfO2 Thin Films , 2012 .

[3]  Byung-Gook Park,et al.  Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec , 2007, IEEE Electron Device Letters.

[4]  Tomislav Suligoj,et al.  Analytical models of front- and back-gate potential distribution and threshold voltage for recessed source/drain UTB SOI MOSFETs , 2009 .

[5]  Jun Xu,et al.  Investigation of Negative Capacitance Gate-all-Around Tunnel FETs Combining Numerical Simulation and Analytical Modeling , 2017, IEEE Transactions on Nanotechnology.

[6]  M. Tang,et al.  Temperature effect on electrical characteristics of negative capacitance ferroelectric field-effect transistors , 2012 .

[7]  H.-S.P. Wong,et al.  Extreme scaling with ultra-thin Si channel MOSFETs , 2002, Digest. International Electron Devices Meeting,.

[8]  Jean-Pierre Colinge,et al.  CMOS circuits made in thin SIMOX films , 1987 .

[9]  Chenming Hu,et al.  Ultra-thin body SOI MOSFET for deep-sub-tenth micron era , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[10]  S. Datta,et al.  Use of negative capacitance to provide voltage amplification for low power nanoscale devices. , 2008, Nano letters.

[11]  Yogesh Singh Chauhan,et al.  Compact Modeling of Drain Current, Charges, and Capacitances in Long-Channel Gate-All-Around Negative Capacitance MFIS Transistor , 2018, IEEE Transactions on Electron Devices.

[12]  Osami Sakata,et al.  The demonstration of significant ferroelectricity in epitaxial Y-doped HfO2 film , 2016, Scientific Reports.

[13]  K. K. Young.  Short-channel effect in fully depleted SOI MOSFETs , 1989 .

[14]  Chenming Hu,et al.  Sub-60mV-swing negative-capacitance FinFET without hysteresis , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).